In a NAND flash memory, all or half of plural cells arranged in a row direction each are connected to write and read latch circuits through a bit line. A write or read operation is performed on all or half of the plural cells arranged in the row direction (for example, cells equivalent to 2 to 8 kB) at one time.
Units of writing and reading are referred to as pages, and one block is constituted by plural pages. Erasure of memory cells is performed in units of blocks. In an erase operation, electrons are pulled out of memory cells, thereby making threshold voltages negative. In a write operation, electrons are injected into memory cells, thereby setting threshold voltages to be positive.
Recently, a multi-level memory has been developed in which one of plural threshold voltages (hereinafter also referred to as threshold levels) is set to enable storage of data constituted by multiple bits. For example, when four threshold levels are given, 2-bit data can be stored in one cell. When eight threshold levels are given, 3-bit data can be stored in one cell. Further, when sixteen threshold levels are given, 4-bit data can be stored in one cell.
Meanwhile, there is a tendency that capacitive coupling between adjacent cells increases as elements are more micronized. Therefore, there is a problem that a threshold level of a cell which is written first changes when an adjacent cell is written. Therefore, there has been proposed that, when data is read from a word line WLn, data from a word line WLn+1 which is written after a word line WLn is read, and a read voltage for the word line WLn is corrected depending on a level of the data (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2004-326866).
However, an erasure level of cells connected to the word line WLn varies depending on a level of the word line WLn−1 written before the word line WLn. Therefore, there is a problem that a read margin for cells connected to the word line WLn decreases. Therefore, there is a demand for a semiconductor memory device which can suppress any influence of capacitive coupling with adjacent cells and accurately read even when an erasure level changes.